1. Field of the Invention
The present invention is related to a switching power supply, more particularly to an adaptive dead time power supply.
2. Description of the Prior Art
A power supply powers electronic equipment. Practicability, efficiency, and size are usually the most concerned features. In numerous power supply topologies, LLC (inductor-inductor-capacitor) is one of the topologies able to implement zero-voltage switching to reduce switching loss. Comparing to other topologies, LLC is also able to output a current to a load twice in one switch cycle and thus improving output voltage regulation. LLC topology also has less EMI problem for the energy contained in the harmonic frequency of input current is quite small. Therefore, LLC topology is very popular in the market nowadays.
FIG. 1 is a diagram illustrating a prior art of LLC topology and LLC controller 30. A bridge rectifier 12 is coupled to two nodes of AC mains for providing a voltage VIN of 100V to 260V on a high power line IN. A high-side power switch 14 is coupled between the high power line IN and a connection node VS, and a low-side power switch 16 is coupled between the connection node VS and a ground power line. Two inductors 18, 20 and a capacitor 22 are coupled in series and between the connection node VS and the ground power line constituting an LC resonant circuit. In every LC resonant period, power is induced to inductors 24, 26 to power a load 28 alternatively.
The LLC controller 30 controls the high-side power switch 14 and the low-side power switch 16. A self boost circuit comprises a diode 32 and a self boost capacitor 34 so as to maintain a voltage VB of a boost power line VB to substantially at a voltage higher than a voltage VS of the connection node VS by VDD. The voltage VDD is a voltage of an operation power line VDD. A high-side driver 36 generates a voltage signal VHSG to drive the high-side power switch 14; a low-side driver 38 generates a voltage signal VLSG to drive the low-side power switch 16. An oscillation controller 40 controls the timing sequence of the high-side power switch 14 and the low-side power switch 16. Because the voltage VS may be as high as 100V, the oscillation controller 40 controls the high-side driver 36 through a level shifter 42.
FIG. 2 is a timing diagram illustrating voltage signals of VS, VHSG, and VLSG from top to bottom. During a pull high section TH, the voltage signal VHSG is logic 1; the voltage signal VLSG is logic 0; the high-side power switch 14 is short circuited and the low-side power switch 16 is open circuited; the voltage Vs is substantially equal to the voltage of VIN. During a pull low section TL, the high-side power switch 14 is open circuited and the low-side power switch 16 is short circuited, the voltage Vs is substantially equal to the voltage of 0V of the ground power line. A dead time section TFD is located in a time slot after the pull high section TH and before the pull low section TL. A dead time section TRD is located in a time slot after the pull low section TL and before the pull high section TH. In order to implement lossless switching of zero-voltage switch, the dead time TFD and the dead time TRD must be controlled properly.
In FIG. 1, the LLC controller 30 comprises a slope detector 41. A capacitor 44 is used to detect the voltage Vs and to provide corresponding signal to the oscillation controller 40 so as to determine time lengths of the dead time TFD and the dead time TRD.